Spike budgets, MLX kernels, and a configurable accelerator

The persistent embarrassment of spiking neural networks has been that the accuracy story keeps catching up to dense ANNs while the energy story keeps drifting. This paper argues the two are linked: SNNs that match ANN accuracy do so by burning a spike budget that quietly approaches dense activation in disguise. The proposed fix is a learnable per-neuron firing rate target, shaped during training by a budget-aware loss term that penalizes overshoot but is permissive about undershoot.

The interesting result is not the headline accuracy match — that has been claimed before — but the continual-learning behavior. When new tasks arrive, the budget terms reshape silently. Neurons that were near-quiet on Task 1 fire more on Task 2 without the architecture being told which neurons belong to which task. The authors interpret this as soft task-allocation pressure emerging from the budget itself, not from any explicit gating.

The engineering implication is that “neuromorphic-friendly continual learning” no longer has to choose between catastrophic forgetting and a runtime spike count that defeats the purpose. The next test is whether the budget-allocation behavior survives on actual neuromorphic substrates, where firing-rate constraints are not soft regularizers but hard hardware limits.

SNN training has historically been throttled by the irregular memory-access patterns that spike-trains produce. CUDA implementations spend a startling fraction of their wall time on the gather/scatter that connects sparse activation to dense weights. The mlx-snn project argues that Apple’s MLX, with its zero-copy unified memory model, sidesteps the pathology entirely.

The benchmark numbers are early but suggestive. On a 4-layer recurrent SNN trained on the N-MNIST event dataset, an M3 Pro completes an epoch in 38 seconds against PyTorch-on-the-same-machine at 142 seconds and PyTorch-on-a-V100 at 89 seconds. The 4× headline rises to 7× on larger event-driven workloads where the gather/scatter dominates.

The non-obvious consequence is that the bottleneck of SNN research may stop being “do I have GPU budget” and start being “do I have a recent Mac.” For a field that has stayed small partly because compute access is uneven, that is a structural change. The first cohort of student researchers who don’t need a university cluster to iterate on a spiking model arrives next semester.

The neuromorphic hardware conversation has been bracketed by two extremes: research-grade event-driven chips that handle sparse spike trains beautifully but stumble on the dense matrix operations that still anchor most real SNN workloads, and conventional neural processors that ignore the temporal structure of spikes entirely. Flexi-NeurA argues the deployable workloads live in the middle — and proposes a fabric that can be reconfigured per layer.

The core claim is that the configuration cost is paid at compile time, not runtime. A toolchain analyzes the target SNN, partitions layers into “event-routed” or “matrix-multiplied” execution modes, and emits an accelerator configuration. The chip itself is silicon-uniform; the routing decides what computational substrate each layer experiences.

The figure that should make hardware investors pay attention is power-per-inference at production-relevant model sizes: 18 mW for a ResNet-equivalent SNN on Speech Commands, against ~600 mW for the same model on a Jetson Orin Nano. If the silicon costs are tractable, this is the first credible argument that neuromorphic deployment can be a procurement decision and not a research-project decision.